1. Field of the Invention
The present invention relates to a semiconductor electronic device using nitride based compound semiconductor and a method for manufacturing the same.
2. Description of Related Art
Electronic devices such as field effect transistors using nitride based compound semiconductors expressed by chemical formula AlxInyGa1-x-yAsuPvN1-u-v (wherein, 0≦x≦1, 0≦y≦1, 0≦y≦1, 0≦x+y≦1, 0≦u≦1, 0≦v≦1, u+v<1), for instance GaN based compound semiconductors, have attracted attention as solid state devices that operate even under high temperature environments near 400° C. Unlike Si or GaAs, it is difficult for GaN based compound semiconductor to prepare single crystal substrates with large diameter. Therefore, electronic devices using GaN based compound semiconductor are prepared from substrates comprised of, for example, silicon carbide (SiC), sapphire, zinc oxide (ZnO) or silicon (Si). Large diameter substrates comprised of Si can be obtained at a low cost in particular and are very beneficial as substrates for electronic devices.
However, since there is a considerable difference in the lattice constant and coefficient of thermal expansion of Si and GaN, a great tensile strain is subtended on the GaN layer when the GaN layer is directly grown epitaxially on the Si substrate leading to development of concave warp and deterioration of the crystallinity over the entire epitaxial substrate on which the GaN layer is grown epitaxially. In addition, cracks are developed on the GaN layer if the underlying strain is large. Consequently, a buffer surface is usually arranged between the Si substrate and GaN layer as a strain-relieving layer. A laminated structure of GaN layers and AlN layers is effective as such buffer layer (refer to Patent Document 1 and 2).
The method of manufacturing GaN based field effect transistors described in Patent Document 1 involves epitaxial crystal growth such as MOCVD process on a 4 inch diameter (101.6 mm) substrate comprising Si single crystal, wherein AlN layer is first formed at a substrate temperature of around 1000-1100° C., and thereafter, a composite lamination is formed as a buffer layer by laminating GaN layers and AlN layers at about the same temperature. Thereafter, a semiconductor operating layer is formed by sequentially laminating an electron transit layer, an electron supply layer and a contact layer on a buffer layer and then separated into each device after forming source electrode, drain electrode and gate electrode. Thus, GaN layer can be grown epitaxially on a Si substrate without any cracks and with excellent crystallinity by making a buffer layer of a composite lamination of GaN layers and AlN layers. In addition, the warp over the entire epitaxial substrate is also improved. Moreover, the buffer layer is not just limited to a composite lamination of GaN layers and AlN layers, and a similar effect can be obtained if an appropriate amount of strain is present even if a composite lamination of AlGaN layers having a different chemical composition with respect to each other is used.    [Patent Document 1] Japanese Patent Application JP2003-59948 A1    [Patent Document 2] Japanese Patent Application JP2007-088426 A1
Incidentally, electronic devices with low on-resistance are crucial to make power supply devices using electronic devices with epitaxial layers of GaN based compound semiconductors.
Since electron mobility decreases if there is dislocation in the semiconductor crystal, it is necessary to decrease the dislocation density as far as possible especially in the semiconductor operation layer so as to decrease the on-resistance. Here, although the threading dislocation, that is developed in the vicinity of the substrate due to the strain between the substrate and the epitaxial layer and which extends in the upward direction, decreases by disappearing in the buffer layer having a composite lamination as described above, there is some threading dislocation that extends up to the semiconductor operation layer also. Therefore, there is a demand for a technology that will further decrease the dislocation density in the semiconductor operation layer in order to decrease the on-resistance of the electronic devices even more.